FIG. 1 is a schematic illustration of a conventional memory system 100 with memory modules MM1 and MM2. The memory system 100 includes a board 110 on which a memory controller 120 and the memory modules MM1 and MM2 are installed. Each of the memory modules MM1 and MM2 includes a plurality of memory chips MC. The memory controller 120 transmits signals to the memory modules MM1 and MM2 via signal lines R1, R2, and R3 on the board 110. The signal lines R1, R2, and R3 may be metal lines or electrical lines through which electrical signals are transmitted.
In general, as the integration density of a circuit board increases, it is becoming difficult to equalize the lengths of signal lines connecting a memory controller to a memory module. If the lengths of the signal lines are different from one another, signals transmitted via the signal lines, for example R1,R2, and R3 in FIG. 1 have different signal characteristics.
In FIG. 1, the signal lines R1, R2, and R3 are bent to equalize the routing distances of a signal transmitted from the memory controller 120 to the memory module via the signal lines R1, R2, and R3. However, in this case, impedance mismatching or a transmission delay in the signal lines R1, R2, and R3 may occur.
FIG. 2 is a schematic illustration of a conventional memory system 200 with memory modules MM1 and MM2. The memory system 200 includes a circuit board 210 on which a memory controller 220 and the memory modules MM1 and MM2 are mounted. In FIG. 2, signal lines R1 and R2 are bent many times to equalize the routing distances of a signal transmitted from the memory controller 220 to the memory modules MM1 and MM2 via the signal lines R1 and R2. Thus, impedance mismatching or a transmission delay in the signal lines R1 and R2 may also occur.
FIG. 3 is a schematic illustration of a conventional memory module 300. The memory module 300 includes a plurality of memory chips MC, and a module tap MTP which is configured to receive a signal and transmit the signal to the memory chips MC.
The routing of signal lines R1 through R3 illustrated in FIGS. 1 and 2 can cause transmission delays and/or distortion of signal characteristics for signals transmitted via signal lines R1 through R3. Unfortunately, due to limited circuit board “real estate,” there are limited numbers of ways to route signal lines between memory controllers and memory modules on a circuit board in order to overcome transmission delays and signal characteristics distortion.